Printed circuit boards (PCB) and printed wiring boards (PWB) are used in a variety of circuits and electrical devices. Many such boards are multi-layer boards, wherein the boards have specific conductive circuit patterns and circuit traces and are arranged in a stacked configuration and interconnected to operate together.
One typical method of electrically connecting together the individual boards of a multiple board arrangement is by using plated through holes (PTH). Plated through holes are essentially holes that extend through the multiple layers and intersect the circuit patterns of the multiple layers. The through holes are plated, such as with a conductive metal, to electrically connect the circuit patterns of adjacent layers together. For example, one layer of a multi-layer arrangement might be fully metallized to act as a grounding layer or ground reference for the other layers of the board. Plated through holes are then positioned to extend from the ground layer to the circuit traces of another layer to provide a ground reference for those circuit traces.
Multi-layer PWBs are used for a variety of RF applications, such as to form RF filters and amplifier circuits that are used for a variety of various RF communication applications. In a typical design, a top and bottom conductor layer might sandwich a middle conductor layer that contains multiple conductor patterns. Interposed dielectric layers separate the conductive layers from each other, both physically and electrically. Plated through holes extend through the conductor layers and dielectric layers and intersect the conductor traces of the pattern of the middle layer. The plated through holes form a conductive interconnection between the traces of the middle layer and the top and bottom conductor layers.
FIG. 1 illustrates one typical multi-layer assembly 10. The assembly 10 forms an RF circuit called an interdigital filter. The filter 10 includes a top conductive layer 12, a bottom conductive layer 16 and a middle conductive layer 14 that includes a circuit pattern that includes multiple traces 20. Dielectric layers 13, 15 separate the conductive layers 12, 14, 16. The traces 20, which form resonators in the filter 10, are coupled at ends thereof to the conductive layers 12, 16 by plated through holes 22 that are sometimes referred to as plated vias. In the case of the filter 10, if the top and bottom conductive layers are grounded, the plated through holes act to ground the selected ends of the resonator traces 20. At RF frequencies, the traces 20 arranged as shown and grounded by the through holes, operate as an RF filter element. Signals at input trace 24 are filtered and output at the output trace 26.
In the filter example of FIGS. 1 and 2, the resonator traces 20 and PTH vias 22 are used to create resonator elements for the filter. To that end, it is very important to have proper alignment between the PTH vias that extend through all of the multiple layers and the respective resonator patterns that are intersected by the vias. Any errors in the registration of the PTH vias with respect to their positioning and intersection with the resonator patterns is undesirable because such errors cause undesirable differences in the resonant frequencies of the subject resonators 20 of the filter 10.
One particular problem in such a multi-layer PWB component design is the fact that the PTH grounding vias are normally added to a PWB device after all layers are bonded together. Referring again to FIG. 1, such a view shown is essentially an “x-ray” view showing the middle layer. However, in reality when the solid conductive layers 12, 16 and dielectric 13, 15 layers are assembled, it is very difficult to accurately locate the PTH vias with respect to the resonator pattern 20 because direct visual reference to the pattern 20 on the middle conductive layer 14 is blocked or covered by the upper dielectric layer 13 and top conductive layer 12. Errors in the absolute position of the PTH grounding vias may cause unacceptable tuning errors in the filter. FIG. 2 shows a typical single resonator conductor pattern and its PTH ground via.
Therefore, there is a need in the art to address problems in the fabrication of multi-layer PCB and PWB devices, and specifically to address the need for PTH placement wherein direct visual references are obstructed. There is a particular need to address positioning of PTH grounding vias in such multi-layer designs which form circuits that are susceptible to degradations and errors resulting from registration errors between the PTH vias and conductor patterns. These needs and others are addressed by the invention.